One conventional single-core system includes a device that predicts a cache hit rate and controls the clock frequency of a CPU based on the predicted hit rate. The single-core system further includes technology that adds into a program, an instruction to designate a clock frequency according to the predicted hit rate. Further, a single-core system may includes a device that refers to cache hit information, supplies a clock signal to a bus controller and an external interface circuit when these circuits operate and suspends the supply of the clock signal to these circuits in the case of the cache hit. With respect write-back processing of writing data from the cache to an external memory, a technology exists that executes the write-back processing during a period in which a task under the control of an operating system is not being executed. Further, a technology exists that monitors bus traffic and the temperature of a bus device, and accordingly set the bus clock.
For examples of such technologies, refer to Japanese Laid-Open Patent Publication Nos. 2004-260274, 2008-250572, 2008-305201, and 2001-325007; and Published Japanese-Translation of PCT Application, Publication No. 2008/001671.
Conventionally, in a case of performing parallel processing in a multi-core system in which plural processor cores access common memory (shared memory) by way of an external input/output (I/O) bus, however, there has been the following problem. When the tasks are executed at each processor core, the operating system does not know whether a cache miss will occur. Therefore, the clock frequency of the external input/output bus is fixed at the highest frequency so that if a cache miss in read access occurs, the data can be read out quickly from the shared memory. Namely, even when access of the shared memory is infrequent and when high speed access of the shared memory is not necessary, the external input/output bus is operated at high speed. Therefore, there has been a problem of wasteful power consumption.